1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a memory device with vertical transistors and a fabrication method thereof.
2. Description of the Related Art
FIG. 1 is a layout of a conventional memory device with vertical transistors and deep trench transistors. As shown in FIG. 1, a plurality of deep trench capacitors 10 are formed in the substrate (not shown), and the deep trench capacitors formed in adjacent rows are staggered. A plurality of word lines 12 are disposed above the columns of the deep trench capacitors respectively, along the vertical direction. A control gate (not shown) is disposed between each deep trench 10 and each word line 12, and is electrically coupled to the word line 12 thereon. A plurality of active areas 14 are formed in the substrate along the horizontal direction. Each active area 14 is disposed above one row of the deep trench capacitors 10, and overlaps the control gates thereunder.
Although the deep trench capacitors shown in FIG. 1 are rectangular, in fact, trench capacitors are actually octagonal due to the semiconductor fabrication process, as shown in FIG. 2A. FIG. 2B shows a misalignment between the active area 14 and control gate in a deep trench capacitor 10. FIG. 3A is an enlarged view of the region 19 in the FIG. 2B. Typically, the region 21 is a gate oxide layer of a transistor (not shown), and region 23 is a portion of an active area 14 and is composed of Si. The region 25 composed of polysilicon is another portion of the active area 14 and serves as the gate of the transistor (not shown). The region 27 is a deep trench isolation composed of silicon oxide. FIG. 3B shows a silicon on isolation (SOI) structure. As shown in FIG. 3A, the regions 21, 23, 25 and 27 form an SOI structure. FIG. 3C shows the relationship between threshold voltage and the thickness of a silicon transistor with an SOI structure. In a memory device as shown in FIG. 3A, the silicon thickness of the transistor with an SOI structure may decrease when a misalignment occurs between the active areas 14 and the control gate on the deep trench capacitors 10. When this condition is met, an angle of the lateral surface 141 of the active area 14 relative to lateral surface 29 of the region 21 is θ1 and is not equal to 90°. The smaller angle θ1 the smaller thickness W. Consequently, the threshold voltage of the vertical transistor (not shown) is reduced as the thickness W is reduced, as shown in FIG. 3C.
In view of this, memory devices with vertical transistors and deep trench capacitors suffer a decrement in threshold voltage of the vertical transistors, and further, current leakage or malfunctions due to misalignment of active areas and control gates on the deep trench capacitors thereof may occur.